1. Field of the Invention
This invention relates generally to hardware design, and more particularly to building configurable designs synthesizable to gates with hardware description and verification languages.
2. Description of the Related Art
In the design of hardware logic, testing and verification through simulation is essential. As such, logic designs typically are specified utilizing a hardware descriptive language (HDL), such as Verilog or SystemVerilog, which are standard IEEE hardware descriptive languages. Verilog and SystemVerilog provide textual formats for describing hardware circuits and systems, which can be used for verification through simulation, timing analysis, test analysis (testability analysis and fault grading), and logic synthesis. These HDLs can be utilized to describe, verify, and simulate the operation of the hardware design.
FIG. 1 shows an exemplary prior art process 100 for manufacturing hardware logic designs. Following the prior art methodology 100, an HDL model of the hardware logic device is created using an HDL language, such Verilog or SystemVerilog HDL, in operation 102. Generally, the HDL model is used to describe what the design does. Once fully described and modeled using the HDL language, the HDL model is run though a series of simulation tests, in operation 104. The test cases are written utilizing the same HDL utilized to model the hardware logic device. The design can then be altered and optimized based on the simulation results.
Once the HDL model is optimized and has passed the test cases of operation 104, the HDL model is synthesized to a register transfer level (RTL) model, in operation 106. RTL defines a logic circuit's behavior in terms of the flow of signals or transfer of data between registers, and the logical operations performed on those signals. The RTL model describes how the design does the functions described in the HDL model. The RTL can later be converted to a gate-level description of the circuit using a logic synthesis tool.
Once synthesized to an RTL model, the RTL model is run though a series of simulation tests, in operation 108. As above, test cases are written utilizing the same language utilized to model the hardware logic device. The design can then be verified based on the simulation results.
After all testing, the device is manufactured in operation 110. As mentioned above, the RTL is synthesized to a gate-level description of the circuit using a logic synthesis tool. Thereafter, placement and routing tools utilize the gate-level description to create a physical layout for the device, which is used in the manufacturing of the device.
Generally, application specific integrated circuit (ASIC) developers need to tape-out their designs in six to eight months to remain competitive in the marketplace. However, as ASIC designs become more complicated, ASIC developers are becoming unable to reach this goal because redesigning all the components of increasingly complex chips takes longer and longer. To remedy this, ASIC developers have turn to third party “ready-made” designs for many of the individual subsystems of the ASICs.
For example, in designing memory subsystems an ASIC developer may purchase ready-made memory controller designs from a third party subsystem developer. The purchased memory controller design can then be integrated into the overall ASIC design. Thus, from the subsystem developer point of view, being able to accommodate a plurality of customer requests is beneficial. However, customer requests often vary from one ASIC developer to the next. As a result, subsystem developers often are required to redesign their subsystems to fit the specific requests of each customer. Accompanying the effort of the redesign, the subsystem developers also need to re-verify the design. In general, the verification effort incurs generating additional test stimulus and changes to the testing infrastructure.
One conventional approach to addressing this issue has been to design programmable general purpose subsystems. A programmable general purpose subsystem, such as a programmable general purpose memory controller, allows the customer to program the individual features of the subsystem to fit into the overall ASIC design. Unfortunately, all the features of a programmable general purpose subsystem generally are not all utilized in any specific design. As a result, unused features will be present on the overall chip, using valuable resources and space that could be better utilized for more useful elements.
Moreover, programmable general purpose subsystems still have clearly defined interfaces that cannot be altered. As a result, the customer is required to design their systems to conform to these interfaces. This conformity can often increase the customer's design costs or make the programmable subsystem unusable to the customer who cannot alter their predefined interfaces.
In view of the foregoing, there is a need for systems and methods for building configurable designs synthesizable to gates. The methods should provide highly configurable designs that allow for interface configurability and do not require the customer to program the device for particular uses. Moreover, the methods should allow the design to be configured to a specific use, and not include extraneous features not requested by the customer.